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Detection and Prevention of Critical Races in Finite State Machines Driving Glitch-Sensitive Receivers (Masterthesis)

10.04.2018

Arunita Mukhopadhyay


10.04.2018, 14:30, room 3945

Abstract:

A combinational circuit containing a functional hazard may generate a glitch due to a race of signal transitions. A race occurring in the output logic of a Finite State Machine (FSM) may be critical when it is used to control glitch-sensitive receivers. This report discusses an algorithm to detect the critical transitions that might lead to glitches in the output of the FSM. Once detected, the report discusses an algorithm to prevent these critical transitions from occurring. This is done by finding a modified state encoding of the FSM so that its output logic is free from functional hazards. The report also discusses the software implementation of these algorithms.



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