Hierarchical Statistical Static Timing Analysis Considering Process Variations
Herr Bing Li
As semiconductor devices continue to scale down, process variations become more relevant for circuit design. Facing such variations, statistical static timing analysis is introduced to model variations more accurately so that the pessimism in traditional worst case timing analysis is reduced. Because all delays are modeled using correlated random variables, most statistical timing methods are much slower than the traditional corner-based timing analysis. To speed up statistical timing analysis, we propose methods to extract timing models for three common circuit types respectively. In order to use the extracted timing models in hierarchical designs, we propose a method to incorporate the correlation between modules by replacing independent random variables. This correlation strongly affects the delay distribution of the hierarchical design according to our experimental results. Because the extracted timing models are much smaller than the original circuits, timing analysis using them is much faster compared to previous approaches using flat netlists directly.;;Bing Li is from Institute for Electronic Design Automation, where he has been working toward the PhD degree since 2004. His research areas include statistical/static timing analysis and circuit optimization. He received his Bachelor and Master degrees from Beijing University of Posts and Telecommunications in 2000 and 2003 respectively.