ReconOS: Multithreaded Programming for Reconfigurable Systems on Chip


Prof. Marco Platzner (Universit├Ąt Paderborn)


The rising density and heterogeneity of field-programmable gate arrays (FPGAs) enable the implementation of complete reconfigurable systems on a single chip. While such reconfigurable systems on chip integrate processor cores, reconfigurable logic cores, fixed-function cores, memories and interconnects, there is still a lack of efficient programming models. Especially reconfigurable logic cores and the feature of partial hardware reconfiguration are not yet sufficiently supported by design methodologies and tools.

In this talk we present ReconOS, an ongoing project that aims at providing a programming model and execution environment for reconfigurable systems on chip. ReconOS bases on the open source operating systems eCos and Linux, and extends the widely-used multithreading programming model across the software/hardware boundary. First, we discuss the novel concept of hardware threads and show their interaction with the operating system. Then, we turn to the ReconOS execution environment which utilizes Xilinx VirtexIIPro and Virtex4 FPGA technology and facilitates partial hardware reconfiguration. Finally, we present performance data and overheads for ReconOS services and report on an object tracking case study.


Marco Platzner is Professor for Computer Engineering at the University of Paderborn. Previously, he held research positions at the Computer Engineering and Networks Lab at ETH Zurich, Switzerland, the Computer Systems Lab at Stanford University, USA, the GMD - Research Center for Information Technology (now Fraunhofer IAIS) in Sankt Augustin, Germany, and the Graz University of Technology, Austria. Marco Platzner holds diploma and PhD degrees in Telematics (Graz University of Technology, 1991 and 1996), and a ''Habilitation'' degree for the area hardware-software codesign (ETH Zurich, 2002). His research interests include reconfigurable computing, hardware-software codesign, and parallel architectures.