High-Level Design Laboratory
High-level design tools such as Matlab Simulink are increasingly being considered in the design of embedded systems. In particular, as the complexity grows, it becomes very difficult to develop and maintain embedded software. In this context, generating code from high-level models such as state automata is gaining in importance.
In this lab, participants learn how to use modern high-level design tools to develop applications and algorithms for embedded systems. The main objective of this lab is to control a baking line (i.e., a model factory). Depending on system requirements and timing constraints, it will be necessary to implement some parts of the embedded system in hardware (VHDL/programmable logic) and some other parts in software, which are then run on a microprocessor. The hardware platform is a Xilinx Zynq SOC.
- 5 SWS, 6 ECTS-Credits
- Room 3971, RCS, 3rd floor
- The registration is only possible via TUMOnline.
- The compulsory introduction lecture takes place on May 2nd 2017, 1:15pm in room 4981. Registered students who do not attend at that lecture will loose their seat and the next student on the waiting list will get the seat.
- The maximum number of participants is 12.
- This lab is based on the same case study (viz., the baking line) as the Microcontroller Systems lab (Mikroprozessorsysteme). However, the focus here is on high-level design flows.
- Written report and oral exam at the end of the lab.
- Knowledge of hardware architectures.
- Programming C and VHDL (even if the code is automatically generated from a model, it is recommended to have knowledge of VHDL and C).
- Basic knowledge of Matlab Simulink and Stateflow is also helpful.
Lecture Slides, reading materials, exercises etc. will be available on Moodle! A TUMOnline account is required to access the e-learning course. If you do not have a TUMOnline login, please contact me.
The students are split up on two lab days, since the room can only accommodate that much.
The two groups will have their lab hours on Monday from 13:15pm to 18:15pm or Tuesday from 13:15pm to 18:15pm
We try to account for the groups preferences and may be able to move the scheduled dates, which will be discussed in during the compulsory introduction.
Nils Heitmann; Room 3942