Development of a Hardware Framegrabber for Network (GigE Vision) Cameras and Evaluation of fast Image Processing Algorithms for Visual Servoing Applications
Master's Thesis / Diplomarbeit
Begin: By arrangement
Control Systems commonly use "simple" sensors that directly quantify the required measure (e.g., angle, temperature, voltage, ...).
Today, however, more and more Control Systems rely on vision-based sensors (i.e., cameras) to allow for more complex and less intrusive control scenarios. In contrast to "simple" sensors, vision-based systems require additional processing power to extract the required measure from the camera images. As the Image Processing Algorithms are part of the control loop, their processing time (delay) and variation therein (jitter) has to be considered and monitored carefully.
Furthermore, as the Vision-based sensing won't be 100% accurate, the resulting error has to be incorporated into the design flow.
To investigate these challenges, a test setup based on a Levitating Ball is being developed.
The goal of this thesis is to develop a Vision-based Control system for a Magnetic Levitating Ball (plant) on a Xilinx Virtex 6 FPGA.
The position of the Levitating Ball shall be sensed using a High-Speed Ethernet Camera (GigE Vision). An Image Processing System shall be implemented on a Xilinx Virtex 6 FPGA to extract the Ball's position from the Video Stream. As a classical CPU-based FPGA-System (using, e.g., a Microblaze Soft-Core) won't be able to process the incoming Video Stream in Real-Time, a Hardware-accelerated Implementation is required for - at least - Image Acquisition and an initial Preprocessing Stage. The CPU then receives the reduced data stream, determines the position of the Levitating Ball and performs the actual control computation. Finally, the control output is sent to the actuator of the Levitating Ball via Ethernet.
- Familiarization with the FPGA platform and its development tools
- Familiarization with the Ethernet Camera
- Implementation of an Image Acquisition Softcore on the FPGA
- Frame Reception via Ethernet
- Region-of-Interest (ROI) selection
- Transfer (partial) image to FIFO
- Evaluation of suitable Image Processing Algorithms and Implementation (in Hard- and/or Software)
If time permits the work can be extended as follows:
- Interfacing the Camera Controls (exposure, shutter, ...)
- Implementation of a simple controller (in Software)
- Much more...
- Profound Knowledge of C and VHDL (incl. synthesis to FPGAs)
- Experience in embedded and hardware programming
- Basic knowledge of Ethernet, TCP/IP and Image Processing is helpful, but not necessarily needed
- Diligent, independent and well-organized work performance
Feel free to get in touch with Martin Geier.