Precision Timed Computing in the Synchronous Setting
Prof. Partha S. Roop (University of Auckland, New Zealand)
Design of time critical embedded systems is usually based on the theory of real-time systems. While such theory is sound, the implementation of such systems on speculative processors leads to many possibilities of errors. In this talk, we propose an alternative approach based on Precision Timed (PRET) architectures. PRET architectures guarantee precise timing without sacrificing throughput. I will focus on a recent synchronous C variant called PRET-C for programming PRET architectures. We map logical time in PRET-C to physical time using static timing analysis. Benchmarking results show that the proposed approach provides a scalable and efficient mechanism for realizing precision timed systems.
Partha is a Senior Lecturer and is currently the Program Director of the Computer system Engineering program. His research interests are in the area of Embedded Systems, Real-Time systems and static timing analysis. He is particularly interested in static analysis techniques for validation, safety and certification. Partha is an Associate Editor of Elsevier Journal on Embedded Hardware design (MICPRO) and EURASIP Journal on Embedded Systems. In 2009, he received the Alexander von Humboldt fellowship for experienced researchers from the Humboldt foundation, Germany and worked with Prof. Reinhard von Hanxleden of CAU, Kiel.