Power Aware Generation of an Embedded CPU (Masterthesis)


Benedikt Backs

30.04.2014, 14:30, room 3945


Shorter development cycles and reduction of circuit power consumption
become more and more important to the semiconductor industry. To face
these challenges two new approaches shall be examined here. One is the
power reduction through dynamic low power techniques within a
microprocessor. The focus lies on clock gating and power gating which
will be used dynamically while run-time. As gating rule the
instruction set is employed. The other main issue is automated
generation of RTL code by metamodeling. That is defining a design and
the desired power saving methods on a higher abstraction level and to
generate the low level RTL description as automatically as possible. A
metamodel is used to capture the structure of a model and to
auto-generate a tool chain. This contains the potential to design ICs
faster and more flexible. As examination object a MIPS-like
microprocessor is generated out of a data model. The MIPS instruction
set architecture plays a key role in the energy aware design. The
microprocessors energy efficiency is enhanced by implementation of low
power techniques within the CPU. By power analysis the different
designs are rated in terms of energy efficiency and compared to each
other. Circuit area and timing is
also subject of investigation. Finally the advantages and pitfalls of
the new concepts are shown.