anticache

Software Caches - Emulating Cache Behaviour in Software

25.11.2015

Prof. Preeti Ranjan Panda


25.11.2015,14:00,  room 3999

Abstract:

In this talk we will discuss the concept of Software Cache, its implications, and the opportunities it provides to compilers targeting Scratch Pad Memory (SPM) or software-controlled memory based systems. Data cache functionality is emulated in software on a part of the SPM; such structures are useful when standard SPM allocation strategies cannot be used due to hard-to-analyze memory reference patterns in the source code.  Software Caches have longer access times, but retain the advantages (present in hardware caches) of exploiting spatial and temporal locality discovered at run-time. We will discuss strategies that consider the presence of software caches in SPM space, and make decisions on which data should be accessed through it, at which times. Our evaluation of the strategy on a Cell processor based machine shows significant speedups over conventional techniques.

Biography:

Preeti Ranjan Panda received his B. Tech. in CSE from the IIT Madras, and his MS and PhD degrees from the University of California at Irvine. He is currently a Professor in CSE Department at IIT Delhi. He has previously worked at Texas Instruments and Synopsys. His research interests are: Embedded Systems Design, CAD/VLSI, Post-silicon Validation, Memory Architectures and Optimisations, and Low Power Computing. He is the author of two books: 'Memory issues in Embedded Systems-on-chip: Optimizations and Exploration' and 'Power-efficient System Design'. Prof. Panda has served as a member of the editorial boards of IEEE TCAD, ACM TODAES, and IJPP, and as Program Co-chair of CODES+ISSS. He has also served on the program committees and chaired sessions at several conferences in the areas of Embedded Systems and EDA, including DAC, ICCAD, and DATE.