Micro-architectural Techniques for Power Management (Masterthesis)


Gautham Nayak Seetanadi

31.03.2015, 16:00, room 3045


Power Management in processors has become an important field in modern day chip design. Channel widths are decreasing and clock speeds increasing. With increasing clock speeds the power consumption also increases substantially. Battery technology has not scaled as well as chip technology resulting in a scarcity of power available for mobile devices. As a result low power designs have great importance in modern day VLSI design. There are two main types of power dissipation in processors, Dynamic power and Leakage power. Dynamic power dissipation is caused due to the switching of transistors in the circuit.Leakage power that dissipates during the sleep time of the transistors are referred to normally as standby leakage whereas the power consumed during operation is referred to as active leakage. Power gating and Clock gating are the two main techniques used in modern day processors in order to combat power dissipation. Clock gating is used to reduce Dynamic power dissipation whereas power gating is used to reduce Static Power dissipation. Modern day programs generally contain many FOR loops.  This thesis aims to use the for loops in order to better enhance the power savings using a separate power saving module. This module can be inserted in a superscalar architecture so as to identify what modules in the EXECUTE stage are used in the FOR loop and then switch off the unused modules leading to greater power savings. This research can help in solving one of the big concerns for Power gating which is the large switch off and break even times for the multiplier unit.